This disclosure relates generally to the field of 3-dimensional integrated circuit design.
Integrated circuits (ICs) are becoming increasingly more complex in design in function. 3-dimensional integrated circuits (3D ICs) are designed to increase the amount of available resources in an IC, allowing for more complex function. A 3D IC comprises two or more chips connected directly to each other. The connection may be either face-to-face or bottom-to-top. Chips used in a 3D IC may comprise any type of circuit structure; however, if the two chips are designed to be interconnected, it may not be possible to test the chips before they are attached to each other. After the chips are attached to each other to form the 3D IC, the chips may not be separated without damaging the chips. This may result in a low yield of working final 3D ICs, as a good bottom chip may be attached to a bad chip before testing. For example, if a top chip and a bottom chip each have a typical 30% yield of good chips from manufacturing, after connecting randomly selected chips, the final 3D IC will have a 9% yield (30% of 30%), tripling production costs of the 3D IC.
The number of wiring layers in an IC increases with the complexity of the IC, as the silicon density of the IC is limited by the amount of available wiring resources. However, increasing the number of wiring layers may have limited benefits as wires located on an upper wiring layer need to be re-powered by a buffer with pins on a bottom layer. Vias are used to connect an upper wiring layer to any lower wiring layers, blocking wiring channels on the wiring layers in between. The vias required for each additional wiring layer in an IC may block 12-15% of the available wiring channels in each layer below; this effect is called via blockage, and is a particular problem in advanced ICs with a large number of wiring layers.